Description: This book is a self-contained introduction to all aspects of microelectronic (IC) testing. It includes the theory necessary for advanced students as well as reference to industrial practice and economics that will interest designers in industry. Chapters cover both digital circuit testing and the growing area of mixed circuits, used particularly in signal processing.
Description: Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints. Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.
Description: Logic synthesis enables VLSI designers to rapidly lay out the millions of transistors and interconnecting wires that form the circuitry on modern chips, without having to plot each individual logic circuit. It is an indispensable tool in the industry today. This first clear and comprehensive guide to logic synthesis techniques spotlights not only the synthesis of two-level, multilevel, and combinational circuits, but also their testability. Written by highly respected experts in both industry and academia, this easy-access tutorial is sure to be the professional reference of choice for designers of next generation VLSI chips.
