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Search Results:
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Displaying records 61 through 70 of 460 |
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Price: $34.99
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Sale: $21.06
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Manufacturer: Prentice Hall PTR
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Number of Items: 1
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Binding: Paperback
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Author: Mark D. Birnbaum
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Publisher: Prentice Hall PTR
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Dewey Decimal Number: 621
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Publication Date: 2003-10-11
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Reading Level: 256
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Description: Today, we take for granted many electronic products such as cellular phones, digital cameras, personal stereos, and printers. But none of these microchip-based electronic products would be possible without the essential (but mostly unknown) Electronic Design Automation (EDA) software tools engineers use to create them. Introduction to Electronic Design Automation gives an overview of the EDA business in the context of the electronic product and semiconductor industries it supports. It covers both the business aspects and the engineering issues addressed by EDA tools, described in layperson's terms.While addressing non-technical readers, the book can also help many technical employees needing the "big picture".
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Price: $42.00
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Sale: $31.92
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Manufacturer: Materials Research Society
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Number of Items: 1
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Binding: Hardcover
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Publisher: Materials Research Society
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Dewey Decimal Number: 620
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Publication Date: 1988-04
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Price: $183.00
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Sale: $171.70
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Jin-Gyun Chung::Keshab K. Parhi
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.3815324
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Publication Date: 1995-11-30
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Reading Level: 240
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Description: Pipelined Lattice and Wave Digital Recursive Filters uses look-ahead transformation and constrained filter design approaches. It is also shown that pipelining often reduces the roundoff noise in a digital filter. The pipelined recursive lattice and wave digital filters presented are well suited where increasing speed and reducing area or power or roundoff noise are important. Examples are wireless and cellular codec applications, where low power consumption is important, and radar and video applications, where higher speed is important. The book presents pipelining of direct-form recursive digital filters and demonstrates the usefulness of these topologies in high-speed and low-power applications. It then discusses fundamentals of scaling in the design of lattice and wave digital filters. Approaches to designing four different types of lattice digital filters are discussed, including basic, one-multiplier, normalized, and scaled normalized structures. The roundoff noise in these lattice filters is also studied. The book then presents approaches to the design of pipelined lattice digital filters for the same four types of structures, followed by pipelining of orthogonal double-rotation digital filters, which eliminate limit cycle problems. A discussion of pipelining of lattice wave digital filters follows, showing how linear phase, narrow-band, sharp-transition recursive filters can be implemented using this structure. This example is motivated by a difficult filter design problem in a wireless codec application. Finally, pipelining of ladder wave digital filters is discussed. Pipelined Lattice and Wave Digital Recursive Filters serves as an excellent reference and may be used as a text for advanced courses on the subject.
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Price: $209.00
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Sale: $144.99
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: A.J. van Roosmalen::J.A.G. Baggerman::S.J.H. Brader
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.38152
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Publication Date: 1991-03-31
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Reading Level: 237
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Description: This volume is dedicated to the field of dry (plasma) etching, as applied in silicon semiconductor processing.
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Price: $79.95
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Sale: $5.00
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Manufacturer: Wiley-Interscience
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Number of Items: 1
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Binding: Hardcover
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Author: Qing K. Zhu
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Publisher: Wiley-Interscience
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Edition: 1
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Dewey Decimal Number: 621.395
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Publication Date: 2004-02-19
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Reading Level: 207
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Description: A hands-on troubleshooting guide for VLSI network designers The primary goal in VLSI (very large scale integration) power network design is to provide enough power lines across a chip to reduce voltage drops from the power pads to the center of the chip. Voltage drops caused by the power network's metal lines coupled with transistor switching currents on the chip cause power supply noises that can affect circuit timing and performance, thus providing a constant challenge for designers of high-performance chips. Power Distribution Network Design for VLSI provides detailed information on this critical component of circuit design and physical integration for high-speed chips. A vital tool for professional engineers (especially those involved in the use of commercial tools), as well as graduate students of engineering, the text explains the design issues, guidelines, and CAD tools for the power distribution of the VLSI chip and package, and provides numerous examples for its effective application. Features of the text include: * An introduction to power distribution network design * Design perspectives, such as power network planning, layout specifications, decoupling capacitance insertion, modeling, and analysis * Electromigration phenomena * IR drop analysis methodology * Commands and user interfaces of the VoltageStorm(TM) CAD tool * Microprocessor design examples using on-chip power distribution * Flip-chip and package design issues * Power network measurement techniques from real silicon The author includes several case studies and a glossary of key words and basic terms to help readers understand and integrate basic concepts in VLSI design and power distribution.
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Price: $89.95
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Sale: $89.95
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Manufacturer: Inst of Electrical &
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Binding: Hardcover
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Publisher: Inst of Electrical &
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Dewey Decimal Number: 621.395
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Publication Date: 1995-05
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Reading Level: 528
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Manufacturer: Academic Pr
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Binding: Hardcover
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Author: Ravi Shankar::Eduardo B. Fernandez
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Publisher: Academic Pr
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Publication Date: 1989-05
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Reading Level: 469
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Price: $62.95
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Sale: $39.45
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Manufacturer: GWV-Vieweg
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Number of Items: 1
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Binding: Paperback
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Author: P.P. Chakrabarti::Pallab Dasgupta
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Publisher: GWV-Vieweg
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Edition: 1
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Dewey Decimal Number: 621
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Publication Date: 1999-06-29
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Reading Level: 134
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Description: Solutions to most real-world optimization problems involve a trade-off between multiple conflicting and non-commensurate objectives. Some of the most challenging ones are area-delay trade-off in VLSI synthesis and design space exploration, time-space trade-off in computation, and multi-strategy games. Conventional search techniques are not equipped to handle the partial order state spaces of multiobjective problems since they inherently assume a single scalar objective function. Multiobjective heuristic search techniques have been developed to specifically address multicriteria combinatorial optimization problems. This text describes the multiobjective search model and develops the theoretical foundations of the subject, including complexity results. The fundamental algorithms for three major problem formulation schemes, namely state-space formulations, problem-reduction formulations, and game-tree formulations are developed with the support of illustrative examples. Applications of multiobjective search techniques to synthesis problems in VLSI, and operations research are considered. This text provides a complete picture on contemporary research on multiobjective search, most of which is the contribution of the authors.
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Price: $175.00
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Sale: $116.00
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Angela Krstic::Kwang-Ting (Tim) Cheng
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Publisher: Springer
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Edition: 1st
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Dewey Decimal Number: 621.395
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Publication Date: 1998-10-31
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Reading Level: 208
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Description: With the ever-increasing speed of integrated circuits, violations of the performance specifications are becoming a major factor affecting the product quality level. The need for testing timing defects is further expected to grow with the current design trend of moving towards deep submicron devices. After a long period of prevailing belief that high stuck-at fault coverage is sufficient to guarantee high quality of shipped products, the industry is now forced to rethink other types of testing. Delay testing has been a topic of extensive research both in industry and in academia for more than a decade. As a result, several delay fault models and numerous testing methodologies have been proposed. Delay Fault Testing for VLSI Circuits presents a selection of existing delay testing research results. It combines introductory material with state-of-the-art techniques that address some of the current problems in delay testing. Delay Fault Testing for VLSI Circuits covers some basic topics such as fault modeling and test application schemes for detecting delay defects. It also presents summaries and conclusions of several recent case studies and experiments related to delay testing. A selection of delay testing issues and test techniques such as delay fault simulation, test generation, design for testability and synthesis for testability are also covered. Delay Fault Testing for VLSI Circuits is intended for use by CAD and test engineers, researchers, tool developers and graduate students. It requires a basic background in digital testing. The book can used as supplementary material for a graduate-level course on VLSI testing.
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Price: $266.00
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Sale: $154.37
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.395
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Publication Date: 1985-10
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Reading Level: 296
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Displaying records 61 through 70 of 460
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