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Search Results:
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Displaying records 171 through 180 of 460 |
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Price: $199.00
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Sale: $119.74
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Gang Qu::Miodrag Potkonjak
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621
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Publication Date: 2003-02-28
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Reading Level: 210
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Description: The development and implementation of intellectual property (IP) protection mechanisms is of crucial importance for the emerging reuse-based system design methodology. Maybe even more importantly, it is such an elegant scientific and engineering challenge that it has drawn a lot of attention from academia and industry in recent years. Intellectual Property Protection in VLSI Designs: Theory and Practice provides an overview of the security problems in modern VLSI design with a detailed treatment of our newly developed constraint-based protection paradigm for the protection of VLSI design IPs from FPGA design to standard-cell placement, from high-level synthesis solutions to gate-level netlist place-and-rout, and from advanced CAD tools to physical design algorithms. The problem of VLSI design IP protection is much more challenging than the protection of multimedia contents or software, and our protection paradigm is also conceptually different from the state-of-the-art approaches in those domains. The key idea in this newly developed IP protection paradigm is to superimpose additional constraints that correspond to an encrypted signature of the designer to design/software in such a way that quality of design is only nominally impacted, while strong proof of authorship is guaranteed. It consists of three integrated parts: constraint-based watermarking, fingerprinting, and copy detection. Its correctness relies on the presence of all these components. In short, watermarking aims to embed signatures for the identification of the IP owner without altering the IP's functionality; fingerprinting seeks to provide effective ways to distinguish each individual IP users to protect legal IP buyers; copy detection is the method to trace improper use of the IP and demonstrate IP's ownership. Intellectual Property Protection in VLSI Designs: Theory and Practice contains the mathematical foundations for the developed IP protection paradigm, detailed pseudo-code and descriptions of its many techniques, numerous examples and experimental validation on well-known benchmarks, and clear explanations and comparisons of the many protection methods.
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Price: $182.00
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Sale: $164.58
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Anand Raghunathan::Niraj K. Jha::Sujit Dey
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Publisher: Springer
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Edition: 1st
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Dewey Decimal Number: 621.381044
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Publication Date: 1997-11-30
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Reading Level: 200
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Description: High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.
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Price: $110.00
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Sale: $110.00
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Manufacturer: Institute of Electrical & Electronics Enginee
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Number of Items: 1
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Binding: Paperback
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Author: Fla.) IEEE Computer Society Workshop on VLSI (2000 : Orlando
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Publisher: Institute of Electrical & Electronics Enginee
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Edition: 2000
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Dewey Decimal Number: 621.395
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Publication Date: 2000-08
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Reading Level: 161
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Description: These conference proceedings are taken from the IEEE Computer Society Workshop on VLSI 2000 (WVLSI 2000). Contents include: system level design methods and examples; low power design; software system design and design environment; advances in multiplier design; and more.
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Price: $80.00
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Sale: $80.00
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Manufacturer: Ieee Computer Society
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Binding: Paperback
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Publisher: Ieee Computer Society
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Dewey Decimal Number: 621.395
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Publication Date: 1986-10
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Reading Level: 607
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Price: $84.00
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Sale: $84.00
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Manufacturer: Institute of Electrical & Electronics Enginee
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Number of Items: 1
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Binding: Paperback
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Publisher: Institute of Electrical & Electronics Enginee
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Dewey Decimal Number: 621
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Publication Date: 1997-04
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Reading Level: 486
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Description: VISI signal processing components of portable systems in communications are described. System, equipment, and component designs for low power and small size critical to product success are described. Applications to the wireless network adn cellular communications are given.
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Manufacturer: Taylor & Francis
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Number of Items: 1
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Binding: Hardcover
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Author: Jesshope
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Publisher: Taylor & Francis
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Edition: 1
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Publication Date: 1986-01-01
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Reading Level: 286
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Description: This book, the first to deal wholly with the topic of wafer scale integration, is the edited proceedings of a workshop held at the University of Southampton in July 1985. As the first international meeting held on this subject it attracted many participants from Europe and the United States. The meeting was particularly timely as there has recently been a renewed interest in research and commercial exploitation of wafer scale integration. The papers presented in the book cover the whole range of topics important in wafer scale integration, beginning with a critical review of fault-tolerant chips and wafer scale integration. Sections on general problems and interconnection strategies follow. There are then six papaers on architectures and four on restructurable very large scale integration. The book concludes with three reviews of different aspects of testability.
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Price: $182.00
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Sale: $9.89
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Allen M. Dewey::Stephen W. Director
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.395
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Publication Date: 1990-05-31
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Reading Level: 228
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Manufacturer: W.H. Freeman & Company
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Number of Items: 1
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Binding: Hardcover
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Author: Jeffrey D. Ullma
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Publisher: W.H. Freeman & Company
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Dewey Decimal Number: 621.38173
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Publication Date: 1984-01
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Reading Level: 495
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Price: $209.00
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Sale: $135.80
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.395
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Publication Date: 1992-12-31
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Reading Level: 128
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Description: Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
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Price: $199.00
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Sale: $81.96
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Manufacturer: Springer
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Number of Items: 1
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Binding: Hardcover
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Author: Stephen W. Director::Wojciech Maly::Andrzej J. Strojwas
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Publisher: Springer
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Edition: 1
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Dewey Decimal Number: 621.395
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Publication Date: 1989-11-30
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Reading Level: 308
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Displaying records 171 through 180 of 460
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