|
Search Results:
|
Displaying records 141 through 150 of 460 |
|
|
|
|
|
|
|
|
|
 |
|
Price: $178.00
|
|
Sale: $52.00
|
| |
|
Manufacturer: Springer
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Hardcover
|
|
Publisher: Springer
|
|
Edition: 1
|
|
Dewey Decimal Number: 621.395
|
|
Publication Date: 2002-04-30
|
|
Reading Level: 296
|
|
|
|
Description: This volume is the third in a series. It brings together a selection of the best papers from two international electronic design language conferences in 2001. The conferences are the Hardware Description Language Conference (HDLCon) in USA; the Forum on Design Languages (FDL), in Europe. The papers cover a range of topics, including: - HDL specification and modelling languages including results from standardisation process: from specialised languages such as VHDL and Verilog to general purpose languages such as C++ (SystemC, SpecC) and Java; - Analogue and mixed signal specification and design; - System on chip, real time and embedded specifications; - Real life experiences in using HDLs; - and EDA vendors point of view describing future design tools that tilise HDLs, such as Web design environments, simulation, verification and synthesis tools. The results presented in these papers will help researchers and practising engineers to keep abreast of developments in this rapidly evolving field.
|
|
|
|
|
|
|
|
 |
|
|
Price: $70.00
|
|
Sale: $70.00
|
| |
|
Manufacturer: Institute of Electrical & Electronics Enginee
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Paperback
|
|
Publisher: Institute of Electrical & Electronics Enginee
|
|
Dewey Decimal Number: 621.3950287
|
|
Publication Date: 1993-04
|
|
Reading Level: 365
|
|
|
|
|
|
|
|
|
|
 |
|
|
Price: $212.00
|
|
Sale: $207.76
|
| |
|
Manufacturer: Springer
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Hardcover
|
|
Author: Andrew B. Kahng::Gabriel Robins
|
|
Publisher: Springer
|
|
Edition: 1st
|
|
Dewey Decimal Number: 621.395
|
|
Publication Date: 1994-12-31
|
|
Reading Level: 304
|
|
|
Description: On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts.
Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.
|
|
|
|
|
|
|
|
|
|
|
|
Price: $168.00
|
|
Sale: $168.00
|
| |
|
Manufacturer: Ieee
|
| |
|
|
|
Binding: Paperback
|
|
Author: IEEE International ASIC
|
|
Publisher: Ieee
|
|
Dewey Decimal Number: 621
|
|
Publication Date: 2001-12
|
|
Reading Level: 450
|
|
|
|
Description: This volume contains the conference proceedings of the 2001 IEEE International ASIC Conference and Exhibition.
|
|
|
|
|
|
|
|
|
|
|
|
Price: $135.00
|
|
Sale: $135.00
|
| |
|
Manufacturer: Institute of Electrical & Electronics Enginee
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Paperback
|
|
Publisher: Institute of Electrical & Electronics Enginee
|
|
Edition: 18
|
|
Dewey Decimal Number: 621
|
|
Publication Date: 2000-08
|
|
Reading Level: 500
|
|
|
|
Description: These papers constitute the proceedings of the IEEE VLSI Test Symposium 2000. Subjects covered include: microprocessor test/validation; low power BIST and scan; defect driven techniques; analogue test techniques; temperature and process drift issues; and more.
|
|
|
|
|
|
|
|
|
|
|
|
Price: $238.00
|
|
Sale: $173.74
|
| |
|
Manufacturer: Springer
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Hardcover
|
|
Publisher: Springer
|
|
Edition: 1
|
|
Dewey Decimal Number: 006.3
|
|
Publication Date: 1992-01-31
|
|
Reading Level: 432
|
|
|
|
|
|
|
|
|
|
 |
|
|
Price: $219.00
|
|
Sale: $19.80
|
| |
|
Manufacturer: Springer
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Hardcover
|
|
Author: Jeong-Taek Kong::David V. Overhauser
|
|
Publisher: Springer
|
|
Edition: 1
|
|
Dewey Decimal Number: 621.395011
|
|
Publication Date: 1995-05-31
|
|
Reading Level: 292
|
|
|
|
Description: Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4--6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
Manufacturer: Ablex Pub
|
| |
|
|
|
Binding: Hardcover
|
|
Publisher: Ablex Pub
|
|
Publication Date: 1996-11
|
|
|
|
|
|
|
|
|
|
 |
|
|
Price: $161.00
|
|
Sale: $112.63
|
| |
|
Manufacturer: Springer
|
|
Number of Items: 1
|
| |
|
|
|
Binding: Hardcover
|
|
Author: Vasant B. Rao::David V. Overhauser::Timothy N. Trick::Ibrahim N. Hajj
|
|
Publisher: Springer
|
|
Edition: 1
|
|
Dewey Decimal Number: 621.381730724
|
|
Publication Date: 1988-11-30
|
|
Reading Level: 224
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
|
Manufacturer: Springer-Verlag
|
| |
|
|
|
Binding: Paperback
|
|
Publisher: Springer-Verlag
|
|
Publication Date: 1991-11
|
|
|
|
|
|
|
|
|
|
Displaying records 141 through 150 of 460
|
|
|
|
